| ??? 07/14/12 09:46 Modified: 07/14/12 09:46 Read: times |
#187934 - it's working!!!! Responding to: ???'s previous message |
After days of reading books, fora, xilinx site, studying examples with no progress.
I just now decided to start a simple project from scratch, I used the DCM core gen and few modules to generate high frequency to test my new DSO and horray it worked. I will play around with phase shift and other options of the DCM. I'm double happy because my new DSO is perfect, it can display the DCM jitter around 500psec which is better than specs in the datasheet. But I can't understand why the DCM didn't work before, hope I will figure it out soon. Thanks Mahmood |
| Topic | Author | Date |
| VHDL DCM problem | 01/01/70 00:00 | |
| coregen | 01/01/70 00:00 | |
| Example found in tool itself! | 01/01/70 00:00 | |
| Xilinx DCM | 01/01/70 00:00 | |
| BUFG | 01/01/70 00:00 | |
| re: BUFG | 01/01/70 00:00 | |
| Can you share it? | 01/01/70 00:00 | |
| Basically don't use coregen | 01/01/70 00:00 | |
| Altera and Xilinx , probably lattice soon | 01/01/70 00:00 | |
| Altera joy | 01/01/70 00:00 | |
| USB blaster clones | 01/01/70 00:00 | |
| it's working!!!! | 01/01/70 00:00 | |
| this warning... | 01/01/70 00:00 | |
| I don't know | 01/01/70 00:00 | |
| new warning | 01/01/70 00:00 | |
| contraints | 01/01/70 00:00 | |
| No change to source | 01/01/70 00:00 | |
Timing Constraints | 01/01/70 00:00 | |
| CoreGen FTL | 01/01/70 00:00 |