??? 07/11/12 02:09 Read: times |
#187903 - VHDL DCM problem |
I'm trying to multiply the frequency of spartan-3e 1600k microblaze dev kit using the DCM core generator with no success.
here is my simple code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library UNISIM; use UNISIM.VComponents.all; entity pulsegen is Port ( clkin : in STD_LOGIC; pulseOut : out STD_LOGIC); end pulsegen; architecture Behavioral of pulsegen is COMPONENT myDCM PORT( CLKIN_IN : IN std_logic; CLKFX_OUT : OUT std_logic; CLKIN_IBUFG_OUT : OUT std_logic; CLK0_OUT : OUT std_logic ); end component; signal clkfxout, xxx, clk0out, cigo : std_logic; begin Inst_myDCM: myDCM PORT MAP( CLKIN_IN => clkin, CLKFX_OUT => clkfxout, CLKIN_IBUFG_OUT => open, CLK0_OUT => open ); process (clkfxout) begin if rising_edge(clkfxout) then xxx <= (xxx xor '1'); end if; end process; pulseOut <= xxx; end Behavioral; the synthesizer gives me these wanings: WARNING:Xst:753 - "C:/Projects2012/spartan3e brd/DCM/DCMtry1/try1/try1/pulsegen.vhd" line 25: Unconnected output port 'CLKIN_IBUFG_OUT' of component 'myDCM'. WARNING:Xst:753 - "C:/Projects2012/spartan3e brd/DCM/DCMtry1/try1/try1/pulsegen.vhd" line 25: Unconnected output port 'CLK0_OUT' of component 'myDCM'. WARNING:Xst:2211 - "C:/Projects2012/spartan3e brd/DCM/DCMtry1/try1/try1/pulsegen.vhd" line 25: Instantiating black box module <myDCM>. WARNING:Xst:1780 - Signal <clk0out> is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal <cigo> is never used or assigned. This unconnected signal will be trimmed during the optimization process. However when I implement the design I get this error message: ERROR:NgdBuild:604 - logical block 'Inst_myDCM' with type 'myDCM' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'myDCM' is not supported in target 'spartan3e'. I read the xapp462 which quite nicely describes the DCM but there is no examples how to uses it. Mahmood |
Topic | Author | Date |
VHDL DCM problem | 01/01/70 00:00 | |
coregen | 01/01/70 00:00 | |
Example found in tool itself! | 01/01/70 00:00 | |
Xilinx DCM | 01/01/70 00:00 | |
BUFG | 01/01/70 00:00 | |
re: BUFG | 01/01/70 00:00 | |
Can you share it? | 01/01/70 00:00 | |
Basically don't use coregen | 01/01/70 00:00 | |
Altera and Xilinx , probably lattice soon | 01/01/70 00:00 | |
Altera joy | 01/01/70 00:00 | |
USB blaster clones | 01/01/70 00:00 | |
it's working!!!! | 01/01/70 00:00 | |
this warning... | 01/01/70 00:00 | |
I don't know | 01/01/70 00:00 | |
new warning | 01/01/70 00:00 | |
contraints | 01/01/70 00:00 | |
No change to source | 01/01/70 00:00 | |
Timing Constraints | 01/01/70 00:00 | |
CoreGen FTL | 01/01/70 00:00 |