| ??? 07/13/12 09:27 Read: times |
#187920 - re: BUFG Responding to: ???'s previous message |
Mahmood Elnasser said:
Andy Peters said:
The important thing to remember is that XST is really kinda stupid, and you have to instantiate the BUFGs for all of the DCM inputs and outputs. So, at minimum, you need a BUFG for the input clock (which drives the DCM CLKIN) and a BUFG for each output. So if you use CLK0, CLK2X and CLKFX, you need three more BUFGs. In addition, the output of the CLK0 BUFG should be used to drive the CLKFB input (and set the generic that indicates clock feedback 1X or 2X to 1X). -a What is puzzling me is that these BUFGs are automatically generated by the core gen in the DCM instantiation file, do I have to repeat them in my source? Mahmood No, you don't. Like I said, I have a "template" of sorts of a clocks entity which instantiates the DCM and all relevant BUFGs, which is similar to what the Xilinx Core Generator gives you. Except that I document it better, and the code style doesn't look like it was generated by an idiot. -a |
| Topic | Author | Date |
| VHDL DCM problem | 01/01/70 00:00 | |
| coregen | 01/01/70 00:00 | |
| Example found in tool itself! | 01/01/70 00:00 | |
| Xilinx DCM | 01/01/70 00:00 | |
| BUFG | 01/01/70 00:00 | |
| re: BUFG | 01/01/70 00:00 | |
| Can you share it? | 01/01/70 00:00 | |
| Basically don't use coregen | 01/01/70 00:00 | |
| Altera and Xilinx , probably lattice soon | 01/01/70 00:00 | |
| Altera joy | 01/01/70 00:00 | |
| USB blaster clones | 01/01/70 00:00 | |
| it's working!!!! | 01/01/70 00:00 | |
| this warning... | 01/01/70 00:00 | |
| I don't know | 01/01/70 00:00 | |
| new warning | 01/01/70 00:00 | |
| contraints | 01/01/70 00:00 | |
| No change to source | 01/01/70 00:00 | |
Timing Constraints | 01/01/70 00:00 | |
| CoreGen FTL | 01/01/70 00:00 |