| ??? 07/13/12 15:27 Modified: 07/13/12 15:31 Read: times |
#187926 - Altera and Xilinx , probably lattice soon Responding to: ???'s previous message |
Jez Smith said:
Oh and having messed with xilinx latest version , much prefer altera at the moment, at least they still support modelsim. Regarding coregen I will try your advice and try not to use it, because my code looks exactly like the example and I'm still getting same error message NG604. When I look it up from internet they say remove the coregen xaw file(or whatever) and replace it with vhd file. Since my altera fpga development board is faster than Xilinx I started with it first, but my altera byte blaster driver didn't work with win7 64 bit with latest quartus ii software, spent long time trying to un install driver and reinstall another drivers from internet until I gave up and forced to go xilinx route. My xilinx board gets programmed by usb cable with ease as well as jtag usb downloader works beautifully for I programmed few CPLDs and made some good money. Mahmood |
| Topic | Author | Date |
| VHDL DCM problem | 01/01/70 00:00 | |
| coregen | 01/01/70 00:00 | |
| Example found in tool itself! | 01/01/70 00:00 | |
| Xilinx DCM | 01/01/70 00:00 | |
| BUFG | 01/01/70 00:00 | |
| re: BUFG | 01/01/70 00:00 | |
| Can you share it? | 01/01/70 00:00 | |
| Basically don't use coregen | 01/01/70 00:00 | |
| Altera and Xilinx , probably lattice soon | 01/01/70 00:00 | |
| Altera joy | 01/01/70 00:00 | |
| USB blaster clones | 01/01/70 00:00 | |
| it's working!!!! | 01/01/70 00:00 | |
| this warning... | 01/01/70 00:00 | |
| I don't know | 01/01/70 00:00 | |
| new warning | 01/01/70 00:00 | |
| contraints | 01/01/70 00:00 | |
| No change to source | 01/01/70 00:00 | |
Timing Constraints | 01/01/70 00:00 | |
| CoreGen FTL | 01/01/70 00:00 |