| ??? 12/09/10 09:56 Modified: 12/09/10 09:58 Read: times |
#180026 - According to the datasheet of my CM3 ... Responding to: ???'s previous message |
Jan Waclawek said:
I am a bit lost in the overall logic of the various documents, just deducing that the register in question is PRIMASK (more precisely its bit 0), for which the manuals (in various words) state, that 1 disables "normal" interrupts and that the reset state is 0. That would confirm my findings, namely that interrupts are "enabled globally" after reset. ... the reset value of PRIMASK is indeed zero and exceptions with configurable priority are not globally disabled after reset. However, all interrupts should be disabled at the NVIC level after reset, since the reset value of SETENA is also zero. Note that PRIMASK refers to exceptions, which are not limited to interrupts (i.e. they also include things like memory management faults, bus faults, etc, which the user may want to be able to handle even directly after reset). |
| Topic | Author | Date |
| [ARM] Default state of interrupts | 01/01/70 00:00 | |
| Normally vectorized interrupt controller | 01/01/70 00:00 | |
| but isn't this the case with ALL microcontrollers? | 01/01/70 00:00 | |
| Often three layers of enable | 01/01/70 00:00 | |
| This is the case here (LPC17xx)... | 01/01/70 00:00 | |
| May vary a lot | 01/01/70 00:00 | |
| Not the case anymore for Cortex-M3s. | 01/01/70 00:00 | |
| Startup code? | 01/01/70 00:00 | |
| not startup code, but the after-reset state | 01/01/70 00:00 | |
| Hw-acceleration | 01/01/70 00:00 | |
| According to the datasheet of my CM3 ... | 01/01/70 00:00 | |
... but if we dig deeper to the datasheets... | 01/01/70 00:00 |