A note about multiple interrupts for same device.

The need is way less now than it was 10 years ago. With almost zero cost (chip area, power consumption, ...) most peripherials are very much accelerated. And the ARM chips don't need to bother about software compatibility with 20 year old source code.

Most UART now have FIFO for reaceive and transmit, so buffer overruns/underruns are not a problem anymore. And the high core speeds means that you can quick quickly handle an interrupt in case you need a response time when last character has been received (normally older protocols with not too high baudrates).

Many UART have hw acceleration for bus use, where they can drive a separate pin to switch on/off a transmitter or switch the transceiver between receive and transmit mode.

Many CAN have multiple transmit buffers so the program can insert a number of frames and the chip will all the time prioritize which of the pending frames that have highest priority and that should be sent as soon as the cable is ready to accept the frame.

The SPI interfaces are often more advanced SSP interfaces with support for FIFO and DMA.

Not needing compatibility with old software really helps a lot when taking advantage of advances in process technologies.