| ??? 12/08/10 11:16 Read: times |
#179990 - not startup code, but the after-reset state Responding to: ???'s previous message |
Of course I suspected that interrupts are enabled there. This is why:
I in original post said:
I tried to decipher the disassembled source but can't find anything which would be of that effect. I then also suspected the bootloader - the LPC17xx (and AFAIK other LPCxxxx-s, too) have an UART-based bootloader in ROM, which is executed as first after reset, and only if it does not find a pretext for waiting for bootloading start, they pass the control to user code. However, re-reading the ARM core registers' documentation revealed, that "global interrupts enabled" is the reset state of the relevant registers indeed. As Per said above, the details are not necessarily pertinent to all ARM-based chips and the documentation has to be consulted in each case, however painful the process is. Oliver Sedlacek said:
I've found all sorts of surprising stuff in the startup code (the stuff that executes before main()). This is the sort of thing that makes learning a new micro such a long process. A very valid remark. It would certainly take some time to gain the same level of expertise and confidence we had in the 8051 and other 8-bitters. Jan |
| Topic | Author | Date |
| [ARM] Default state of interrupts | 01/01/70 00:00 | |
| Normally vectorized interrupt controller | 01/01/70 00:00 | |
| but isn't this the case with ALL microcontrollers? | 01/01/70 00:00 | |
| Often three layers of enable | 01/01/70 00:00 | |
| This is the case here (LPC17xx)... | 01/01/70 00:00 | |
| May vary a lot | 01/01/70 00:00 | |
| Not the case anymore for Cortex-M3s. | 01/01/70 00:00 | |
| Startup code? | 01/01/70 00:00 | |
| not startup code, but the after-reset state | 01/01/70 00:00 | |
| Hw-acceleration | 01/01/70 00:00 | |
| According to the datasheet of my CM3 ... | 01/01/70 00:00 | |
... but if we dig deeper to the datasheets... | 01/01/70 00:00 |