| ??? 12/09/10 09:47 Read: times |
#180025 - Not the case anymore for Cortex-M3s. Responding to: ???'s previous message |
Per Westermark said:
The ARM core have a normal and a high-prio interrupt signal, but normally always a vectorized interrupt controller (VIC) connected to these two interrupt signals. So it doesn't really matter if these signals are enabled or not, as long as the VIC starts with the interrupt sources disabled. Cortex M3 interrupt handling is [b]significantly[/b] different from earlier ARM architectures, e.g. ARM7. In the Cortex M3 architecture, the interrupt controller (NVIC - nested vectores interrupt controller) is actually part of the core instead of the core only having rudimentary interrupt handling and requiring an actual interrupt controller to be tacked on by the chip manufacturer. |
| Topic | Author | Date |
| [ARM] Default state of interrupts | 01/01/70 00:00 | |
| Normally vectorized interrupt controller | 01/01/70 00:00 | |
| but isn't this the case with ALL microcontrollers? | 01/01/70 00:00 | |
| Often three layers of enable | 01/01/70 00:00 | |
| This is the case here (LPC17xx)... | 01/01/70 00:00 | |
| May vary a lot | 01/01/70 00:00 | |
| Not the case anymore for Cortex-M3s. | 01/01/70 00:00 | |
| Startup code? | 01/01/70 00:00 | |
| not startup code, but the after-reset state | 01/01/70 00:00 | |
| Hw-acceleration | 01/01/70 00:00 | |
| According to the datasheet of my CM3 ... | 01/01/70 00:00 | |
... but if we dig deeper to the datasheets... | 01/01/70 00:00 |