??? 12/07/10 16:54 Read: times |
#179958 - Normally vectorized interrupt controller Responding to: ???'s previous message |
With many other microcontrollers, you have the interrupt handling interfaced in the processor core. So it is vital to have interrupts disable when setting up the system.
The ARM core have a normal and a high-prio interrupt signal, but normally always a vectorized interrupt controller (VIC) connected to these two interrupt signals. So it doesn't really matter if these signals are enabled or not, as long as the VIC starts with the interrupt sources disabled. The reason for a VIC is to give the processor support for many interupt channels that can share a single interrupt input of the core while still being possible to enable/disable individually, and to be able to control the priority of these individual interupt sources. Turning off interrupts in the core can work as a master switch when the program needs a safe zone for critical updates. With all interrupt channels initially deactivated in the VIC, the processor don't need any extra layer of protection after boot. |
Topic | Author | Date |
[ARM] Default state of interrupts | 01/01/70 00:00 | |
Normally vectorized interrupt controller | 01/01/70 00:00 | |
but isn't this the case with ALL microcontrollers? | 01/01/70 00:00 | |
Often three layers of enable | 01/01/70 00:00 | |
This is the case here (LPC17xx)... | 01/01/70 00:00 | |
May vary a lot | 01/01/70 00:00 | |
Not the case anymore for Cortex-M3s. | 01/01/70 00:00 | |
Startup code? | 01/01/70 00:00 | |
not startup code, but the after-reset state | 01/01/70 00:00 | |
Hw-acceleration | 01/01/70 00:00 | |
According to the datasheet of my CM3 ... | 01/01/70 00:00 | |
... but if we dig deeper to the datasheets... | 01/01/70 00:00 |