Why so huge quote that you don't really make use of? Intentionally wasting bandwidth?


If my answer was irrelevant, that would probably be because your question was irrelevant. The phase detection logic can't be discussed until you have a basic understanding how they work. Your comments about how fast a PC is etc clearly shows your only mental picture of measuring a delay is to run a counter at high speed and check how many ticks from signal A flank to signal B flank.


I bet most other readers would have a pretty good idea about how to measure propagation delays by now.

In this link, the Maxim circuit needs to detect a 0.8ns change from 16.5 to 17.3 ns propagation delay:
http://www.maxim-ic.com/app-notes...vp/id/1903
A difference is that the Maxim circuit (using a 74HC86) has a comparator intended to toggle around a fixed value. When measuring, you instead use an ADC to measure the mean value of the XOR output.

The propagation delay for a 74x04 inverter is:
7404: 12-22 ns low-to-high and 8-15 high-to-low - averages to about 10-18ns
74LS04: 9-15 ns low-to high, 10-15 high-to-low
74HC04: about 7 ns
74HCT04: about 8 ns
74F04: 2.4-5 ns (F series never mentioned anywhere in thread)

As can be seen, overlap of delay ranges means the delay can't be used as single parameter to differentiate family. But the delay values are within the possible range to measure.

And I did say how you could measure the propagation delay:


I just noted that for a simple generic hobby tester, it would not be meaningful to implement the specials for a '161 or '163 since they require that the square wave generator doesn't emit just one frequency but two. The least significant bit will toggle at half the frequency of the clock signal, so to get 1MHz out of Q0, you need 2MHz on the clock input. And for synchronous chips, there is normally a need to have an extra delay line to get proper setup times for some of the signals before the clock signal toggles. The concept is still easy, but it takes programmable logic to allow the routing of such signals to enough pins to make it meaningful which means that it costs more work/money than it is worth for some chips. Letting the hobbyist manually route the the signals could solve the complexity problem - all it would need is a display to inform what signals to route where before starting the propagation delay test.

And if you would have done what I have said several times, you would have seen:
http://commons.wikimedia.org/wiki/File...se-XOR.png

http://pstca.com/spice/phasedet/phasedet.htm (shows two frequencies, but your skill should have made you understand the result with same frequency and varying phase - as in varying propagation delay - instead.

That you again and again have questioned a PC:s ability to see the small time difference between two signals so very clearly shows that you do not know about an XOR-based phase detector. And refuse to read up on them before continuing the debate. You may have heard about them, but don't understand them for some magical reason. You may have seen other detectors, but are totally lost on the use of an XOR to compute phase-to-voltage or to compute the difference frequency between to signals.

You are just digging your own grave if you continue to debate without reading up enough to start discuss specific practical aspects of such a detector. If you know how it works, you would also know what factors that controls the precision of it. You would for example know that the slew rate of the XOR does matter, i.e. that delays that gets close to the slowrate speed reduces the precision which is a reason to get an XOR with fast rise and fall times and good drive capabilities.


Are you saying that you can't mentally convert the text:
"Send square wave at high speed through chip and let delayed and non-delayed signal mix in XOR gate of best available technology. The variation in delay will vary the low-pass-filtered voltage from the XOR."

+-----+        +-----------+          +-----+   +--------+   +-----+
|     |        |  Subject  |          |     |   |        |   |     |
| OSC o---+----o   under   o----------o     |   | low    |   |     |
|     |   |    |   test    |          | XOR o---o pass   o---o ADC |
+-----+   |    +-----------+    /-----o     |   | filter |   |     |
          |                     |     |     |   |        |   |     |
          ---------------------/     +-----+   +--------+   +-----+

The above was totally outside your grasp to visualize on your own?

You have already received links graphically showing input signals and output results.

If the tested subject has very short delays, it may be good to add an extra delay in that chain to not be too close to a zero phase between the two square wave signals. But this is a hobby project so no one will bother about any temperature compensation, keeping track of the length of signal paths, or worry too much about capacitances. Even a lousy implementation will give a change in the analog value for a change in the propagation delay in the tested chip. And bad low-pass filtering resulting in too much ripple can be compensated for a bit by adding software filtering of the ADC values.


So then, Richard: Please show some schematic or block diagram how you have done this a number of times with a PC? Was the PC the phase detector? The ADC? The delay line? Exactly what did you do that made you need a fast PC? You didn't just use the printer port signals to try to measure time, did you?


I just got a very interesting mental image: Richard "handwaving" Erlacher. If having a wiki page on handwaving, there would be a huge debate if handwaving should best be illustrated with Harry Potter or with Richard Erlacher.

Richard handwaving: "XOR's won't verify tristate parts without tying the enables active."
Richard handwaving: But how would you use an XOR for an unknown chip?
Richard handwaving: "If you had a PC that literally ran at a high enough rate that it could change each and every device pin concurrently at a 250 ps step, you could, perhaps, detect timing variations that exist between technologies."
Richard handwaving: "Further, the XOR, being two logic levels, is the slowest of all gates, and will often be too slow for speed-testing."
Richard handwaving: "Most importantly, for an XOR-based gate checker, a known-good sample of the same part is needed."
Richard handwaving: "You'll need lots of storage."
Richard handwaving: "First of all, how would you detect that an output is tristate? How would a square wave and an XOR help with that?"
Richard handwaving: "I don't see how that's relevant either, since the PC isn't capable of making observations at a rate high enough to detect differences in propagation delay, rise time, etc."

You continuously think of XOR as a way to compare two multi-bit test patterns.

All the time failing to notice that the XOR is only used for a single output pin, to compare the propagation delay of the signal out from that pin compared to the undelayed stimuli signal. Totally beside any tests for input/output/tristate/... or what truth table the chip may have.