Doesn't matter if square wave only works for known parts. First step is obviously to perform logic function detection, including such thinkgs as looking for tristated outputs. If do you know it's an '00, you can try to figure out if LS00, HC00, HCT00 etc by starting to play with individual inputs and/or outputs.

It really doesn't matter that an XOR is slow, since the critical part isn't the delay from input change to output change. The critical part is that a change in quotient between the two inputs does change the percentage of time the output is high or low, resulting in an analogue value after low-pass filtering. Even very small changes in time delay on the input does affect the average output voltage. The reason for getting the fastest possible technology for the XOR gate is more that it's good to have fast rise and fall times on the output signal so that the majority of the analog integration is performed in steady states and not during the flanks of the output signal. But even the flanks can be survived since they add the same offset error for a fixed input frequency of the square wave until the quotient gets so bad that the output never goes fully high or fully low before the gate changes output state again.

The precision is best when measuring delays through simple gates, such as an OR gate. Having a more complex subject-under-test means longer delays between the change of an input and the change of an output. This requires a slower square wave and hence less resolution of phase detector. But on the other hand, a chip with slower signal path is normally not allowed to be used in a design that is as sensitive to the chip delays. If you use a ripple counter, you definitely don't want to make a design where 100ps change in ripple time changes the circuit between working and failing. You need to make a design that handles the worst-case ripple time with some margin. More internal layers in the logic chip also makes a working chip have a wider spread so the requirement to measure the ripple delay don't need the same precision as if you measure the delay of a 74x00.

The thing here is that even a hobbyist can get very interesting results with a simple phase detector. It's irrelevant what you can do if you have a 5Gs scope available just for the simple reason that most people don't have one.

A very large number of logic chips of the types we are discussing in this thread - not random CPLD or FPGA - have quite a number of internal parameters that can be "tasted" with quite simple "spoons". For some chips it may be hard to send an input logic signal that results in a suitable output logic signal. But there may be an /OE pin that changes the output. Either between a data value and a fixed logic level or between a data value and tristate.

The discussion I did start about doing some detection instead of just entering a chip ID and test a logic table was that much things can be done with low costs. Low costs (or actually any costs) means you have limitations in what you can do. But low cost can still give lot more results than just walking through 2^n input patterns and watching output values and say a chip is a quad 2-input NAND.

As long as the square wave signal used for phase detection has fixed and known frequency, you can manage some decent calibration of a phase detector with not too advanced methods. So you can get interesting results even without seed chips. The confidence of the tester would of course be better if having measured 100 chips of every model and family, but even when a seen chip hasn't been tested you can still measure time delays with a resolution that is affected by the square wave frequency needed, i.e. what measurement range you set your circuit to use. When you get all the way into considering relativistic tests based on seed chips, you reach a level where you have to consider the differences in delays between batches or manufacturers. But then you have reached a level that should normally not matter - a user should normally not make a design that only works with a Fairchild chip and not a TI chip.


Remember that the tables can still be arranged as a decision tree, so you do not have to test all logic tables even if the chip is of unsupported type. A single detected output means the decision tree can directly prune all chips that has an input at that position. Even with 250 different chips in the database, you probably don't need to test for more than 10 different chips - the other 240 gets pruned on the way. And it isn't until you have done this pruning that you make use of any additional hardware to look for inputs with hysterese, current dirve capabilities, chip power consumption or possible gate delay times.