we produce 1000 units (sensor control system) from our SMT line and when testing the product most of the time from one lot we are bound to have 4-5 failures , wheres the other MCUs of the same lot work properly ? . Though not a big deal what I want to say is there are certain discrepancies that we dont know and cannot gaurantee anything .
This shows the purpose of providing Gaurantee to products or do you just ridiculously design and throw away it in the market? .
we have ZERO failures after the one or two bad joints on one or two of the boards in a lot have been fixed. I think that over ~5000 boards I have seen ONE defective semiconductor. Now, at one time it was much worse, but after installing antistatic measures we achieved the above.

as stated earlier by Neil , It does cause wear . That sows the purpose of wear-leveling algorithm , which people use for their hardcore product design , though not with the port pins but with the memory .
You have no idea, do you? the wear leveling algorithm is applied to flash where there is a finite number of erases possible, that is not 'wear' that is flash technology.

i am not in the favour of running things to its maximum limits ? , where did I say this that I design this way , dont IMPOSE this on me .
I did not impose that on you, but there is no other explanattion for your rants about 'wear'

Erik