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???
11/27/07 18:27
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#147460 - oy
Responding to: ???'s previous message
I don't wish to drag this out any longer ...

but if you don't wish to read data sheets before deciding which device to use, then I can't help you.

I like the DLL's in SP-II's but prefer PLL's (not the crap in FPGA's, but the real thing, for which there are real spec's, acquisition range, acquisition time, tracking range, etc.) when I have to synchronize processes. DCM's, DLL's and Altera's PLL's are of little use when, for example, you have to sync up with one of eight data streams, each driven by crystals that have their own idea of what 80 MHz means.


You misunderstand the intended use of these clocking resources. They are NOT meant (and can't be used for) things like recovering embedded clocks in data streams or locking to any arbitrary incoming clock. I use them to double my global clock so I can read two bytes from a buffer at the same time, and the frequency synthesis is handy for this Camera Link interface I'm working on. With all of these clock managers, you must understand that you need to tell the tools, at synthesis time, the expected input clock frequency and clock multiplication/division (if using the synthesizer and not just the DLL).

As for syncing to eight data streams with the same clock frequency and different phases: I know nothing about your application and really, maybe an FPGA is the wrong thing for your app. But maybe you SHOULD look into Virtex-4 FX or Virtex-5 LXT devices. Maybe these newer (Spartan 2 is positively ancient in FPGA terms) devices will be able to do what you need them to do. They may bust your budget and they don't have 5V tolerance.

Sure, the data sheets are a thousand pages and there's a lot you'll have to learn about before you can get your money's worth out of them.

But if it was easy, everyone would do it, right?

-a

List of 21 messages in thread
TopicAuthorDate
Tri-state busses in FPGAs            01/01/70 00:00      
   Tristate Buffers (TBUFs) have been phased out            01/01/70 00:00      
      Thank you            01/01/70 00:00      
         Closing the loop            01/01/70 00:00      
            siumulate?            01/01/70 00:00      
               I didn't simulate it (yet)            01/01/70 00:00      
                  hmmm            01/01/70 00:00      
                     So ... what about a BIG multi-party bus?            01/01/70 00:00      
                        delay            01/01/70 00:00      
                           nevertheless ...            01/01/70 00:00      
                              re: nevertheless            01/01/70 00:00      
                                 What disappoints me is the advertising vs reality            01/01/70 00:00      
                                    advertising            01/01/70 00:00      
                                       advertising, badvertising ... lies!            01/01/70 00:00      
                                          oy            01/01/70 00:00      
                                             If only one could rely on them ...            01/01/70 00:00      
            largely, it's because it's not an option            01/01/70 00:00      
               Zackly            01/01/70 00:00      
                  If you have internal tristate resources ...            01/01/70 00:00      
                     I have new worries now            01/01/70 00:00      
   tristates in FPGAs            01/01/70 00:00      

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