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???
11/26/07 00:51
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#147394 - So ... what about a BIG multi-party bus?
Responding to: ???'s previous message
... as one might encounter when combining several blocks of on board RAM to form a deeper, wider one? What's the price one has to pay, in quantative terms? With 4-bit LUT's, it's going to be quite a bit of delay, when one needs a 36-bit-wide RAM buffer, 32K-words deep, isn't it? Enough to warrant considering another solution, maybe?

RE




List of 21 messages in thread
TopicAuthorDate
Tri-state busses in FPGAs            01/01/70 00:00      
   Tristate Buffers (TBUFs) have been phased out            01/01/70 00:00      
      Thank you            01/01/70 00:00      
         Closing the loop            01/01/70 00:00      
            siumulate?            01/01/70 00:00      
               I didn't simulate it (yet)            01/01/70 00:00      
                  hmmm            01/01/70 00:00      
                     So ... what about a BIG multi-party bus?            01/01/70 00:00      
                        delay            01/01/70 00:00      
                           nevertheless ...            01/01/70 00:00      
                              re: nevertheless            01/01/70 00:00      
                                 What disappoints me is the advertising vs reality            01/01/70 00:00      
                                    advertising            01/01/70 00:00      
                                       advertising, badvertising ... lies!            01/01/70 00:00      
                                          oy            01/01/70 00:00      
                                             If only one could rely on them ...            01/01/70 00:00      
            largely, it's because it's not an option            01/01/70 00:00      
               Zackly            01/01/70 00:00      
                  If you have internal tristate resources ...            01/01/70 00:00      
                     I have new worries now            01/01/70 00:00      
   tristates in FPGAs            01/01/70 00:00      

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