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???
11/26/07 00:03
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#147392 - hmmm
Responding to: ???'s previous message
Without thinking about it too much, I'd probably say that the way you'd want to code the functionality is like this:

module triState (a,b,sel,out);
input a,b,sel;
output out;

wire out = sel ? a : b;

endmodule

that will give you a mux though not a tristate buffer. I think that what it comes down to is that if you have the hardware resources then the synthesizer would know how to utilize the tri keyword. In all cases if you're set on a tristate buffer you would need to make the wire of type tri. Check out this link:

http://www.altera.com/support/e...state.html

D

List of 21 messages in thread
TopicAuthorDate
Tri-state busses in FPGAs            01/01/70 00:00      
   Tristate Buffers (TBUFs) have been phased out            01/01/70 00:00      
      Thank you            01/01/70 00:00      
         Closing the loop            01/01/70 00:00      
            siumulate?            01/01/70 00:00      
               I didn't simulate it (yet)            01/01/70 00:00      
                  hmmm            01/01/70 00:00      
                     So ... what about a BIG multi-party bus?            01/01/70 00:00      
                        delay            01/01/70 00:00      
                           nevertheless ...            01/01/70 00:00      
                              re: nevertheless            01/01/70 00:00      
                                 What disappoints me is the advertising vs reality            01/01/70 00:00      
                                    advertising            01/01/70 00:00      
                                       advertising, badvertising ... lies!            01/01/70 00:00      
                                          oy            01/01/70 00:00      
                                             If only one could rely on them ...            01/01/70 00:00      
            largely, it's because it's not an option            01/01/70 00:00      
               Zackly            01/01/70 00:00      
                  If you have internal tristate resources ...            01/01/70 00:00      
                     I have new worries now            01/01/70 00:00      
   tristates in FPGAs            01/01/70 00:00      

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