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???
11/25/07 20:39
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#147381 - If you have internal tristate resources ...
Responding to: ???'s previous message
Russ Cooper said:
Richard said:
Do you have an FPGA family that (a) is on the market, and (b) offers internal tristate resources?

a) Yes.

b) No.

So that means NO, right? (see the AND?) If no such thing exists, why worry about it? Now, if you have access to Spartan-II, which I like very much, then you have options.

This echoes what Mike pointed out a few days ago. As you know, I chose a top-down approach to learning all this stuff, and started by hacking away until I got my Verilog model of a Morse code decoder to synthesize and work properly.

I've got a second project in mind now that is (fortunately, I think) raising all kinds of bottom-up questions that kind of have me stuck right now reading the data sheet and asking dumb questions like the one that started this thread. More to follow when I get unstuck.

-- Russ


Back in '78 or so, a HAM friend of mine produced a circuit that generated Morse code from a bipolar (therefore very small) PROM and a counter, to generate the periodically recurring signature for his club's repeater. It produced very precise code at a very reasonable rate. Not being interested in Morse code, myself, I didn't make any other observation.

For outside help with the problem you're working, I'd be looking at the various RLL encoder/decoder SPLD's published out on the www, for a bit of "spiritual guidance" about how one might encode/decode a code with variable character length. I'm not, in any way, criticizing your approach, particularly as the objective is to learn, and I'm sure you're doing that, but I'd certainly recommend examining "prior art" related to what you're doing.

The tristate bus within an FPGA is apparently a thing of the past. It means that whenever the notion of a common bus pops up, there will be a huge timing penalty due to the required concatenation of dozens of logic cells in order to form a single mux wide enough and deep enough to support the requirement. I've seen some people deal with this with an ultra-high-speed serial bus, common to all the parties. That would be fine if you didn't mind having to divide the costly ultra-high bandwidth by the bus width. On devices with lots of pins, the tristate buffers can be external, i.e. each module talking on the common bus can be externally connected. That, of course, has its own price. You know what they say ... "where there's a will, there's mourners ..."

RE









List of 21 messages in thread
TopicAuthorDate
Tri-state busses in FPGAs            01/01/70 00:00      
   Tristate Buffers (TBUFs) have been phased out            01/01/70 00:00      
      Thank you            01/01/70 00:00      
         Closing the loop            01/01/70 00:00      
            siumulate?            01/01/70 00:00      
               I didn't simulate it (yet)            01/01/70 00:00      
                  hmmm            01/01/70 00:00      
                     So ... what about a BIG multi-party bus?            01/01/70 00:00      
                        delay            01/01/70 00:00      
                           nevertheless ...            01/01/70 00:00      
                              re: nevertheless            01/01/70 00:00      
                                 What disappoints me is the advertising vs reality            01/01/70 00:00      
                                    advertising            01/01/70 00:00      
                                       advertising, badvertising ... lies!            01/01/70 00:00      
                                          oy            01/01/70 00:00      
                                             If only one could rely on them ...            01/01/70 00:00      
            largely, it's because it's not an option            01/01/70 00:00      
               Zackly            01/01/70 00:00      
                  If you have internal tristate resources ...            01/01/70 00:00      
                     I have new worries now            01/01/70 00:00      
   tristates in FPGAs            01/01/70 00:00      

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