| ??? 11/27/07 03:51 Read: times |
#147437 - advertising Responding to: ???'s previous message |
Richard Erlacher said:
I'm not after blazing speed, but if I pay an extra hundred bucks (Avnet tells me that is only another 10% of the base price) each for the "fast" family, I want the thing to perform at least as fast as the marketing guy says. That means 5 GHz count rates for a 64-bit synchronous presettable up/down counter, and much faster for the shorter ones. Now we know they can't do that ... Whatever gave you the impression that you can do a 5 GHz counter in any FPGA? Why do you listen to the marketing, anyways? I also want to be able to attain 95% utilization 95% of the time. Most of the time that's not achievable either, at least in terms of marketing department gate counts. Nobody I know pays attention to "gate counts." A useful metric is number of CLBs and number of flops, as well as amount of block RAM. Anyways, when choosing an FPGA, you've really got to read through the data sheets and understand what's going on. Even seemingly obvious stuff like number of I/Os needs to be scrutinized if you're using different I/O voltages. If you want 95% utilization be prepared to do a lot of floorplanning, or at least relax speed requirements. Fortunately, the products I use are reusable, so once I find something I can use, I stick with it. That's why I use the Spartan-II stuff. It's 5-volt tolerant so I don't have to spend the extra $30 plus board space for level shifters. I most generally have kilowatts of power available, so the low-voltages stuff doesn't have any particular appeal. On the other hand, we don't have kilowatts available and we don't have to support legacy 5V stuff. We've moved from Spartan 2E to 3E because quite frankly, the 3E works better for me. (Gotta love DCMs and all of that.) THe clock-to-Q doesn't help since it's just latency at the chip boundary. The internal workings always have additional delays. What about internal clock-to-out? All flip-flops have that spec ... -a |
| Topic | Author | Date |
| Tri-state busses in FPGAs | 01/01/70 00:00 | |
| Tristate Buffers (TBUFs) have been phased out | 01/01/70 00:00 | |
| Thank you | 01/01/70 00:00 | |
| Closing the loop | 01/01/70 00:00 | |
| siumulate? | 01/01/70 00:00 | |
| I didn't simulate it (yet) | 01/01/70 00:00 | |
| hmmm | 01/01/70 00:00 | |
| So ... what about a BIG multi-party bus? | 01/01/70 00:00 | |
| delay | 01/01/70 00:00 | |
| nevertheless ... | 01/01/70 00:00 | |
| re: nevertheless | 01/01/70 00:00 | |
| What disappoints me is the advertising vs reality | 01/01/70 00:00 | |
| advertising | 01/01/70 00:00 | |
| advertising, badvertising ... lies! | 01/01/70 00:00 | |
| oy | 01/01/70 00:00 | |
If only one could rely on them ... | 01/01/70 00:00 | |
| largely, it's because it's not an option | 01/01/70 00:00 | |
| Zackly | 01/01/70 00:00 | |
| If you have internal tristate resources ... | 01/01/70 00:00 | |
| I have new worries now | 01/01/70 00:00 | |
| tristates in FPGAs | 01/01/70 00:00 |