Erik Malund said:

It is about 87 times easier to program something intermitent into a FPGA than it is to do so in a uC.

I'm not at all sure what you've said here, but, somehow, I doubt you know, either.
What I am saying is that the skill to avoid the possibility of some little snag that only raises its ugly head once a week after the thing has been delivered lurking in an amateurishly coded FPGA is much more likely than such happening in an uC. As an example, I have, I do not know how often, found metastability possible under very precise external stimuli in FPAG/CPLD/PLD code.

Erik Malund said:
I can teach someone to program a FPGA in, maybe, a day, to teach someone to program one so that no 'rarely occuring strange things' happen will take, at least, months.

Gee ... it takes me a day just to switch from one vendor's tools to another, and I've done it dozens of times. Unless you're programming a device to be a flipflop or a simple gate, I think there's room for doubt.
I am making the point that while it is relatively easy to learn write the code, say for some MMIO, that 'should' work and probably will - under most circumstances, it is many, many times more difficult to make any FPGA code that WILL work under all circumstances

Remember, too, that you're the guy who doesn't need a cycle-by-cycle simulation of what you do.
Taken out of context, i would make no such statemen about a FPGA.

Erik