This was said before, but rule number one is don't use the term software when speaking about FPGAs. Both Verilog and VHDL are Hardware Description Languages.

To answer your question, you can use truth tables and Karnaugh maps to do FPGA design, but any non-trivial design will take eons to do this way, have many errors in it, and be impossible for someone else to debug/maintain. HDLs allow you to describe things behaviorally and allow the synthesizer to break them down into logic equations for you. As an example, here is a simple up by one, asynchronously reset, 3 bit counter done both with truth tables and behaviorally:

Truth Table Way (2 separate files):

-- file #1: D_FF.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity D_FF is
     Port( 
      clock : in  STD_LOGIC;
      R     : in  STD_LOGIC;
      D     : in  STD_LOGIC;
		
      Q     : out  STD_LOGIC
     );
end D_FF;

architecture Structural of D_FF is

begin

process(R, clock)
begin
	if (R = '1') then
	     Q <= '0';
	elsif rising_edge(clock) then
	     Q <= D;
	end if;
end process;

end Structural;

-- file #2 : counter.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Counter is
     Port(
      clock : in  STD_LOGIC;
      R     : in  STD_LOGIC;
		
      count : out  STD_LOGIC_VECTOR (2 downto 0)
     );
end Counter;

architecture Structural of Counter is

component D_FF is
     Port(
      clock : in  STD_LOGIC;
      R     : in  STD_LOGIC;
      D     : in  STD_LOGIC;
		
      Q     : out  STD_LOGIC
      );
end component;

signal feedback	: STD_LOGIC_VECTOR(2 downto 0);
signal Q        : STD_LOGIC_VECTOR(2 downto 0);

begin

registers : for i in 0 to 2 generate
begin
	
     flip_flops : component D_FF
	Port Map(
	 clock	=> clock,
	 R	=> R,
	 D	=> feedback(i),
			
	 Q	=> Q(i)
	);
			
end generate;


feedback(0) <= not Q(0);
feedback(1) <= ((not Q(1)) and Q(0)) or (Q(1) and (not Q(0)));
feedback(2) <= ((not Q(1)) and Q(2)) or ((not Q(0)) and Q(2)) or ((not Q(2)) and Q(1) and Q(0));

count <= Q;

end Structural;

--------------------------------------------------------------
Behavioral Way (only 1 file):

-- Xilinx_counter.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Xilinx_counter is
     Generic(width : integer := 3); -- behavioral counter can be any size you want simply by changing one number!
     Port(
      clock : in  STD_LOGIC;
      R     : in  STD_LOGIC;
		
      count : out  STD_LOGIC_VECTOR(width-1 downto 0)
     );
end Xilinx_counter;

architecture Behavioral of Xilinx_counter is

signal count_int : STD_LOGIC_VECTOR(width-1 downto 0);

begin

process(R, clock)
begin
     if (R = '1') then
	count_int <= (OTHERS => '0');
     elsif rising_edge(clock) then
	count_int <= count_int + '1'; -- can be an up by X counter by changing just one other number!
     end if;
end process;

count <= count_int;

end Behavioral;

Both were synthesized using the Xilinx ISE tools for a Spartan 3 FPGA and both had exactly the same resource usage and maximum clock frequency (364.79 MHz). This isn't always the case since the Xilinx synthesizer will generally always outperform you unless you understand the multiplexer based structure of an FPGA.




Synthesize and place and route are two completely different steps. Synthesize translates your generic HDL code into a structure that can run inside the target FPGA. Place and route then figures out how to specifically map your sysnthesized design into the target device (what interconnects to use, what LUTs to be loaded, etc.) Without either of these you will never be able to run your design in an actual device.




Xilinx has a free tool called Webpack that can synthesize and place and route for most of its smaller FPGAs in all families. It has no simulator though so you would need to use Modelsim with it.

http://www.xilinx.com/ise/logic...ebpack.htm




- Know the difference between synchronous and asynchronous.

- Understand what setup and hold times are.

- Know the difference between a latch and a flip-flop (hint: avoid latches)

- Know how to design good state machines.

- Understand what is synthesizable and what isn't (most of VHDL is not synthesizable, only simulatable)

- Use generics wherever possible

- Avoid using initial condition declarations (don't map to ASICs well)

- Always use a global reset and only use rising_edge and falling_edge constructs on clock signals

- Most importantly, you are designing hardware NOT software