No. Logic minimization using K maps was something you needed to do when you implemented state machines with a ROM and a counter. Nowadays, the only people who worry about them are the wizards who write synthesis tools.

Basically, as Mike says, you write VHDL code that describes the logic. OK, so it's not quite as simple as that, as there are some specific rules one must follow, but those rules are detailed in various synthesis tool manuals.



Both Altera and Xilinx offer free development tools with which one can implement a design. These tools are: design entry (either a text editor for writing VHDL or Verilog, or a schematic capture if you're crazy), a synthesis tool to translate HDL into gates, and fitter (place and route) tools to fit the gates into the specific chip. Visit their web sites for details.



You are NOT programming FPGAs. Please: get that through your skull.

And, yes, absolutely, learning how to simulate using ModelSim is a vital skill. You will spend probably 80 percent of your FPGA development time using the simulator. You shouldn't even consider running the synthesis/P+R tools until you are satisfied that your design is logically correct.



Again: Altera and Xilinx offer them on their websites.



No, because you can write code that simulates wonderfully well but can't be synthesized, so you'll need to actually build something in hardware.

-a