I've hear that sort of remark for some time, Andy.

I don't speak Verilog, myself, though I may take it up. I don't speak C++ either, though and have gotten by for many years. They didn't have such things when I went to school, and, in fact, they didn't yet have microprocessors or even integrated circuits.

My clients don't speak HDL, generally speaking. A meeting for reviewing a design, particularly the acceptance review, seems to take half a day if the design is presented in schematics, which they (the client's people) can all read and pretty readily interpret, and many times less than that, and about ten days if presented in HDL listings, VHDL, ABEL, etc. They don't like reviewing HDL, I don't like it either. If I show them the dozen-line VHDL code for a BINARY-TO-7-SEGMENT encoder, they get sick. If I show them the gate-level schematic, they like it, even though most of them don't know what it really means.

This afternoon, with a little time on my hands, I spent a few hours with XILINX' ISE v8.1.02. Note that it's been out for a month, yet already has two service packs. I wrote one of the development managers at XILINX a page-long letter including a dozen or more screen-shots showing him what's messed up in the steps required to put two quad flipflops on the schematic and hook up their inputs. There were LOTS of problems, most of them pretty minor, but all of them terribly annoying in view of the fact that, prior ot starting on that exercise, I took two minutes, and i'm not exaggerating here, two minutes, to load and utilize my old 1986 OrCAD SDT for DOS to draw the schematic so I'd have a reference drawing. It didn't even take another minute to print it. The Windows version would have taken 10 minutes or moreto do all that, but the XILINX software took WAY longer, and the issues are still unresolved. Now that's just what I'd encountered in the first .01% of a design.

I've been complaining about non-adherence to standard VHDL also. One example ... if you want to describe a macrocell with feedback, the mode you'd probably think of first is BUFFER, right? Well try using that mode in XILINX' version. I know why it's the way it is, but it's not right. You've no guarantee that it will provide a macrocell with feedback in a CPLD, even if you try as best you can. The only way is ABEL or a schematic.

Now, Altera's not much better if at all. I constantly have service issues open with them as well as with XILINX. I'm of the opinion that it's the squeaky door that gets the oil, and that they'll never fix it if you don't tell 'em it's broken, ... a hundred times.

We all figure out how to work around those "little" problems. However, I hate it when they come out with new tools that work slower, put more emphasis on the "look and feel" of their software than they do on the work product or the time and effort needed to generate it.

I could go on, believe me, but I'm too humane ...

RE