"I find the limitations of LUT widths and the added delays associated with concatenating LUT's in order to build a wide gate a real pain. It's a pain in wide comparators, long synchronous counters, and in wide adders. The extra flops would be handy in a carry-save type."

A handful of points:

a) I do all of my FPGA designs in an HDL (I'm bilingual and speak both Verilog and VHDL, and I've been doing HDLs for over ten years). I'll never go back to schematic entry.

b) as a result of a), I let the synthesis tool do all the heavy lifting. If I want an address decoder, I write a comparator. And I depend on the fact that

c) modern FPGA fabrics are "fast enough" to implement wide decoders and big counters without the floorplanning and hand tweaks that were necessary to get older devices to meet timing, and

d) modern synthesis tools, even the free tools from Brand A and Brand X, are really good at what they do (esp. compared to the absymal tools from ten years ago). The tools really do understand the particular chip resources and will infer RAMs, shift registers and whatever with ease. Of course you have to instantiate black boxes for vendor-specific things like clock PLL/DLLs and you are of course encouraged by the chip vendors to use their IP (FIFOs, DSP blocks, PCI cores, whatever) which also get instantiated as black boxes.

Of course you need to specify completely your timing and area requirements; otherwise the tools will do whatever's quickest.

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