You say,

"Not true any more! Modern devices have enough routing resources to let you use the flip-flop independently of the rest of the logic in the macrocell/slice. This is especially true for FPGAs, where there are a lot of flip-flops and sometimes you need wide logic (address decoders, whatever)."

but I have my doubts.

I find the limitations of LUT widths and the added delays associated with concatenating LUT's in order to build a wide gate a real pain. It's a pain in wide comparators, long synchronous counters, and in wide adders. The extra flops would be handy in a carry-save type.

If it's realistic to use the flipflop associated with, say, a Spartan-II LUT in combination with logic in a different logic cell, I'd appreciate a pointer to an app-note or something. Likewise, if you know where Altera makes that possible in their "standard" FPGA families, e.g. 10K, 20K, etc, (you know, the ones you can still get in qfp's) a pointer to that would be appreciated as well.

As for the CPLD's, well, XILINX and Altera make it pretty plain what the delays are, and, of course, they show up in simulation.

The old MACH series devices from AMD and Lattice didn't have such support, and it's too bad. Their product-term sharing scheme was nice but slow, and a couple of passes through that AND the product term array for your local logic block, and you had a 30 ns propagation in a 10 ns part. Of course, their simulation was only "functional."

RE