True. But what always annoyed me about the CPLD fitter tools until recently is that they would tell you how many logic levels your design required, rather than telling you the maximum clock frequency and/or combinatorial delay time. Cripes, the tools are run on a computer; surely, the computer can't do the hard work of mapping logic levels to delays and give me a number? Oy. Yes, Lattice, I'm talkin' 'bout you!



Except in the cases where you're filling the whole chip and you can't route between sections, but if you blow away pinouts it fits fine. Ugh. Having said that, we always do layouts in parallel with CPLD/FPGA logic design, and rarely (but it still happens) do we run into this problem. It was a lot worse in the Old Days of FPGAs where you really had to let the tools choose the pinout.



Not true any more! Modern devices have enough routing resources to let you use the flip-flop independently of the rest of the logic in the macrocell/slice. This is especially true for FPGAs, where there are a lot of flip-flops and sometimes you need wide logic (address decoders, whatever).

-a