They were "Eraseable" PLD's and really preceded the common terminology of "COMPLEX" PLD's, which is what CPLD is generally understood to mean, since AMD and later Lattice described their MACH series of complex PLD's as a function of how many macrocell blocks, e.g. 18V22 as in 22V10in the terminology derived from PALs.

As they grew in size and complexity various vendors added interconnect matricies that facilitated internal feedback of buried macrocell outputs, product-term sharing, and other useful features. These tended to make the devices slower if one used them, and huge efforts were made to make the input-to-output delays uniform throughout, unlike what one encountered in FPGA's.

The BIG thing with CPLD's as opposed to FPGA's is that the timing is quite deterministic and mostly quite independent of which macrocell is used for which function, while FPGA timing can be severely impacted by signal routing delays. That's why it's easier to use the CPLD's. First of all, you can preassign the pinout with very high confidence that it will work out as you plan. Secondly, you can rely on predetermined timing in nearly all cases.

CPLD's however, have relatively few registers and lots of logic potential. However, in either device type, once you use a register or gate, the entire logic element (or half or quarter element, in some FPGA structures) is used, whether it's an inverter or a tristate flipflop with set/reset and enable.

Though it wasn't always the case, most CPLD's do, now, allow asynchronous (product-term) clocking.

For beginning programmable logic designers, I can't recommend FPGA's unless one is willing to take a long time to learn all the various available architectures. The differences can make large differences in coutcomes in terms of resource utilization and performance. That's not the case with CPLD's, though it's still a good idea to read and understand the device datasheet before starting. I've encountered some rude disappointments when I've been in too big a hurry.

RE