| ??? 02/17/06 12:01 Read: times |
#110221 - Logic 1 to 0 transition Responding to: ???'s previous message |
Kai Klaas said:
We had agreed some weeks ago, that we shouldn't talk about 'modes'. Say instead: "If port is emitting logic low state." Or: "If port output is logic low." Or something similar. yes. Suresh said:
Logical 1 to 0 Transition Current(ITL) (Ports 1,2,3) = -650 µA when VIN = 2V, VCC = 5V ± 10% HOw this should be taken care of while connecting the driver circuit to the port. Kai Klaas said:
This means, that if you want to force a port pin, which was programmed as input by writing '1s' into according SFR, to logic low, that you must take care that source impedance is not too high. Here, less than 2V / 650µA = ca. 3kOhm. Otherwise the potential at port pin will never fall down to less than 2V, which is needed to detect logic low state. Let me take an example: If i have connected a PNP to port1.x. Then iam changing its state from logic 1 to 0. During this operation the PNP should turn 'ON'. At that instant the o/p current at the port(at 2V during transition)will be 650uA thus forming high apposing current and preventing the PNP to sink its base current. Is this what that happens? If so, please tell me how i should work on in my port driver circuit in avoiding (or) to make use of this transition condition. Erik said:
nice copy of the datasheet, where is the question Just tried to show what i understood from the datasheet with an example. to make the discussion clear. Erik said:
WHAT driver circuit, what connection? I need to get clear with the characteristics of the port pins during i/o operations to design the driver circuit appropriately. Thanking you all -suresh. |
| Topic | Author | Date |
| AT89s52 Port pin clarifications: | 01/01/70 00:00 | |
| nice copy, where is the question | 01/01/70 00:00 | |
| output characteristics | 01/01/70 00:00 | |
| most confusing post | 01/01/70 00:00 | |
| Answers | 01/01/70 00:00 | |
| Logic 1 to 0 transition | 01/01/70 00:00 | |
| You haven't read the 'bible' chapter... | 01/01/70 00:00 | |
| no details about transition from logic 1 | 01/01/70 00:00 | |
| other way 'round | 01/01/70 00:00 | |
| There ARE!! | 01/01/70 00:00 | |
| pFET2 | 01/01/70 00:00 | |
| Weak and very weak pull-ups | 01/01/70 00:00 | |
| maintaining low source impedence? | 01/01/70 00:00 | |
| by making thje driver a sink............ | 01/01/70 00:00 | |
| Pull-downs create problems | 01/01/70 00:00 | |
| Maximum IOL per port pin: 10 mA ? | 01/01/70 00:00 | |
| IOL | 01/01/70 00:00 | |
| IOL = 10mA or 1.6mA? in port 1 | 01/01/70 00:00 | |
Depends on load | 01/01/70 00:00 |