Hi Mahmood,

Note that the CD4O46 have a Fmax/Fmin ratio quit less than your need (1:70). Also, in the PLL design, you should keep some VCO room for over/undershooting to avoid unlock. Moreover, with Fref going from 1 to 70 Hz, the damping factor will change accordingly, unless the VCO function frec=F(Vcontrol) is rather logaritmic.

I used circuits like you posted to multiply mains frequency by 1000, to use 1 Hz sampling digital counter, and get mHz reading. But in the 40 to 60 Hz range! (Argentina uses 50 Hz nominal)

IMHO, a uC design will be more compact, functional over the complete range, fast to react, and stable, provide an adequate software design. I worked with and designed hundreds of PLLs, but achive such big Fmin/Fmin ratio is not common, unless changing some element that fixed the range, which is not practical here.

That was my dime contribution

Daniel