It might be "smoother" if you use a '597, as that will absorb some irregularity if you're dead set on using just a shift register. At least this one is double-buffered, unlike the '165.

The MCU is certain to have trouble with the timing because comparing a 20-bit counter, or several shorter ones takes a bit of time. AFter all, you're likely to be using a pixel clock of at least 16 MHz, and you have to divide that by, say, 6 and then by 525 for NTSC sync using interlace ... you get the picture, all the while comparing for the counts that indicate the start of blanking and of sync, and the ends, of course.

However, an MCU that's doing anything at all other than dealing with the timing, and the generation of the sync signals, will have terrible difficulty making the timing exact. It has to be exact, not +/- 2 ns. Irregularity will make the sync timing dodgy and, of course, it will make the pixel position on the display wander back and forth. Noise on the pixel clock will make the display look like water is running from one side to the other.

The concepts are simple enough, but the implementation must be quite precise.

RE