Yes 74LVC4066 is a very nice chip. But it can't be stressed enough that the original 4xxx chip series should be very much avoided unless solving very specific problems. They were a very nice addition when originally released, but their time is in the past and they are not too nice in todays faster and faster environments.

About buffering of signals - this thread is a bit long so it is starting to get hard to remember exactly what information that have been presented, and what haven't been presented. What is known is that the current display will display static patterns for maybe 10 minutes. And high switching noise breaks havoc with the signal integrity. But exactly what clock speeds are used? Besides having correct flanks - are all signals still having correct setup and hold times after being rebuffered through the full chip chain? Each time the flanks of a signal are slow, the timing where the input signal gets detected as high or low may slowly move, resulting in a large change of pulse lengths and their position relative to other signals, slowly eroding the timing margins. While being digital, the absolute levels of signals gets constantly refreshed, but the timing is an analog property that does allow gradually increasing clock skew to affect the system. Rise-time control, schmitt-trigger inputs, and potentially signal termination may help with ringing, but it still takes long enough signals to make the total clock skew low enough that the full chain gets proper timing.