With a brownout detector generating an interrupt (or ADC with good voltage reference) and a bit of caps, you can have the processor check if it has power enough to start at least one more write of suitable size.

Life is reasonably simple with the above and an I2C-connected EEPROM. No real possibility that the processor manages to play on the pins enough to issue a random write while going into (or out of) reset. A parallell RAM on the other hand will react instantly to a spurious pulse.

I once had quite a bit of problems with an old 8031 hw running on dry batteries in case of a power loss. The hw wasn't really good enough to know the remaining power in the batteries, resulting in a number of damaged configurations resulting in ugly error beeps when the checksum was invalid.