Hai,
I was learning about the convolutional encoding.
Went through the process of convolutional coder with constraint length N=3 consisting of N-stage shift register and two modulo-2 Adders for encoding a serial data input.
Here are few from what i understood:
- obtaining coded output bits using the Adders
- The recurrence of the output at particular stages of data input thus leading to cause irrelevence about the first few data input bits while deciding on outputs.

This is been represented as a moore machine using four states (since N=3). Thus the intended logic circuit for convolutional coding could be obtained.

If iam right with the above, I would like to clear few doubts regarging it.
1. I couldnt understand how or, in what logic the shift register is connected to the Adder in order to get the required output bits.

The link below shows the diagram i refered,

http://www.8052.com/users/Suresh/diag.doc

It would be nice if i could get some explanation on it.


Regard's
Suresh.