Hello everyone,
Having decided to do a project for my diploma course in VLSI, i started collecting materials for developing "Viterbi decoder with convolutional encoding" using Verilog.
But iam unable to clearly define what is convolutional encoding, and what is viterbi decoding.
Bowsing the internet doesnt give me any clear definition or idea of what iam suppose to do or how to start with the project
Also iam not quite sure of the selecting the specification.
from the net i got the verilog code for rate 1/2 with hard- decision decoding. Will it be worth to start with.

Requiring your valuble Advice to proceed further.

Regard's
Suresh.