The one advantage of the CPLD over the FPGA, now making the distinction, is that, once programmed, the CPLD doesn't require it be programmed under system power each time the power is turned on. Now, this is a small thing, but, during the power on cycle, when the FPGA is being programmed, some of the I/O's may, in fact, not come up in the correct state. CPLD pins can be programmed to provide full drive current as soon as power comes on, while FPGA pins may not do that. I say may because, unfortunately, one has to read the datasheet to know for certain.

5-volt tolerance isn't terribly important to most guys, these days, but, since I still operate on 20-35-year-old equipment from time to time, I prefer the older devices to having to introduce level shifters. After all, the level shifters require time be added to the I/O prop-delays. Again, this is fairly minor, except in some cases. The devil's in the details, though, don't you agree?

RE