Yet another interesting chip.

Very hard to tell about it from just the datasheet. It has a output acceleration feature to give more current umpfh when it detects a level change, but from a quick browse I don't see they have enough info to really tell how much current or charge that acceleration feature gives, or if it is active until a certain voltage level is reached.

The bad part is that the 4Mbit/s variant does not show so very high capacitances in the diagram, and the 20Mbit/s chip shows support for even less capacitance.

I think standard ribbon cable is somewhere around 20pf/foot or 70pf/meter, so it will be the current drive that will be the limiting factor. But definitely worth getting samples of to evaluate.

The booster feature for level changes is a nice feature since it allows quicker toggling without increasing the amount of current when two outputs are fighting until the chip detects and toggles logic level. The NXP chip did explicitly claim to have a weak output drive to be easy to overrride by another output, but I did not see anything about any boost feature was available to speed up a state change.

If nothing else, this thread ends up with a nice list of interesting leven-conversion alternatives.

It would be truly marvelous if there existed any auto-detect buffer capable of the task.

Individual control? If the data signals can't auto-detect the required data direction, then I would need a chip that is programmable, so I can order it to set D0A as input, D1A, D2A as output, D3A as input, D4A, ... depending on configured peripherial. Having the data direction programmable means a buffer can have strong drive continuously since someone have told the chip that there will be no collision. These auto-detect chips are weaker so a "normal" output will be powerful enough to overrrule the state. Excellent for level conversions locally on a PCB, but unless the boost feature is good enough, it might not be possible for use with ribbon cables.

Anyway - I'll have some datasheets to read through tomorrow

Using microcontrollers as smart buffers would probably be outside the scope because of the need for data in both directions - they would have to run at a serious pace to pick up 8 bits from one port, perform a mapping and masking and emit on other port and then do the same thing in reverse. And guarantee a maximum delay before the master processor tries to pick up the input data and sends out next output data.

A different solution to the problem might be to waste 70+70 pins on the main processor (just within reach in pin count and speed capacity) or FPGA. Let it listen on all signals, while having 70 buffered output channels with individual output enable control. Alas, that is a solution with just as many problems to solve. Just different problems.