| ??? 08/05/10 16:15 Read: times |
#177736 - New answer Responding to: ???'s previous message |
New response from Silabs:
Silabs guy said:
I heard back from our design team regarding the reset of the UART receive state machine. This is the designer's response: It looks like the UART receive state machine can be reset by clearing the receive enable SFR bit and then setting it again. This will reset the receiver, but it will not clear out the data in the receive path de-glitcher. The device would need at least five system clock cycles of inactivity on the RX line to clear this de-glitcher. We haven't simulated this, but you may want to try it as a potentially faster solution than your current one. This is more precise, but I am a little concern about "It looks like...". And five system clocks (in one clocker uC) seems too few time to me. But will try. Daniel |
| Topic | Author | Date |
| Question about UART reset | 01/01/70 00:00 | |
| How to Do It | 01/01/70 00:00 | |
| Re: How to do it | 01/01/70 00:00 | |
| True Confirmation | 01/01/70 00:00 | |
| i have had excellent experience with SILabs in this respect | 01/01/70 00:00 | |
| Silabs response | 01/01/70 00:00 | |
| Insist On Answer From Chip Designer | 01/01/70 00:00 | |
| RE: you get basically bull s**t answers at the first level | 01/01/70 00:00 | |
New answer | 01/01/70 00:00 | |
| I will check... | 01/01/70 00:00 | |
| a solution would be ... | 01/01/70 00:00 | |
| Please, explain... | 01/01/70 00:00 | |
| Rxd | 01/01/70 00:00 | |
| RE: RxD | 01/01/70 00:00 |