The .LST file shows:

  578: 1  0234	D2 AE		        setb  ES1  ; Enable port  1  interrupts.
  579: 1  0236	D2 AF			setb EA ; Global interrupt enable.
 

This looks correct to me.

I wonder whether this is a priority problem. My program never writes to the IP register or any of its bits. This register is supposed to be initialised to zero on reset, which means that interrupts will use their "natural priority". Is this correct?

If so this means that serial port 0 can interrupt the serial port 1 interrupt handler but not the reverse. This should not make any difference in my case since I've only got the serial port 1 interrupt enabled.

From reading the User Guide I conclude that the programmer has no direct control over the priority level that the processor is running at. It will automatically change to the priority level of the interrupt when it vectors to the handler (meaning that it can only be interrupted by a higher priority interrupt), and it will automatically return to the previous priority level when the RETI is executed. Is this correct?

If it is, I can't see anything wrong with the priority scheme I'm using. When running the main loop, the processor should be at the lowest priority. Therefore the RI1 or TI1 bits ought to be able to interrupt it, whatever state the PS1 bit is in.

What am I missing?

Thanks - Rowan