| ??? 05/20/12 18:44 Read: times |
#187448 - Those are actually PALs not CPLDs Responding to: ???'s previous message |
You would need a device with 2048 registers to form a 256x8 prom and then you need extra registers for the counter/control and so on so you would be looking at a larger device from the likes of altera or xilinx.
Once you get into devices that are that large then you might as well start looking at FPGAs with block RAM which could be used to emulate the prom.Its probably not economic unless you implement the entire system as a DDS device in a FPGA |
| Topic | Author | Date |
| 256bit x 8 proms | 01/01/70 00:00 | |
| What frequency Sine wave & Clock ? | 01/01/70 00:00 | |
| Thank you | 01/01/70 00:00 | |
| DDS (Direct Digital Synthesis) | 01/01/70 00:00 | |
| digital sine wave | 01/01/70 00:00 | |
| uC sine generator | 01/01/70 00:00 | |
| DMA | 01/01/70 00:00 | |
| neither do I | 01/01/70 00:00 | |
| ARN | 01/01/70 00:00 | |
| 'F120 Series | 01/01/70 00:00 | |
| Other solutions | 01/01/70 00:00 | |
| 150nS access time is so long | 01/01/70 00:00 | |
| is that realy the case? | 01/01/70 00:00 | |
| Of course my solution | 01/01/70 00:00 | |
| Hmmm.., nice but... | 01/01/70 00:00 | |
| Those are actually PALs not CPLDs | 01/01/70 00:00 | |
| ATF750CL for PT clocks | 01/01/70 00:00 | |
| ATF750 | 01/01/70 00:00 | |
| ATF750C ? | 01/01/70 00:00 | |
| Yes, Jim You are exactly right. | 01/01/70 00:00 | |
| Can I suggest | 01/01/70 00:00 | |
| ATDH1150USB | 01/01/70 00:00 | |
| Update : ATDH1150VPC | 01/01/70 00:00 | |
Thanks JIM | 01/01/70 00:00 |