| ??? 05/18/12 04:13 Read: times |
#187406 - 150nS access time is so long Responding to: ???'s previous message |
Why not take about 1/10th or less in access time by utilizing a real hardware logic FIFO. They have plenty to choose from in the Digikey Library. Just get one with a re-transmit. Load the chip up, create a clock that can be triggered for the reads and synchronizes with your re-transmit, and launch your sequence of parallel digits. Unfortunately, FIFOs can get pretty expensive depending on how aggressive you want to be with resolution and frequency spectrum, in this case. |
| Topic | Author | Date |
| 256bit x 8 proms | 01/01/70 00:00 | |
| What frequency Sine wave & Clock ? | 01/01/70 00:00 | |
| Thank you | 01/01/70 00:00 | |
| DDS (Direct Digital Synthesis) | 01/01/70 00:00 | |
| digital sine wave | 01/01/70 00:00 | |
| uC sine generator | 01/01/70 00:00 | |
| DMA | 01/01/70 00:00 | |
| neither do I | 01/01/70 00:00 | |
| ARN | 01/01/70 00:00 | |
| 'F120 Series | 01/01/70 00:00 | |
| Other solutions | 01/01/70 00:00 | |
| 150nS access time is so long | 01/01/70 00:00 | |
| is that realy the case? | 01/01/70 00:00 | |
| Of course my solution | 01/01/70 00:00 | |
| Hmmm.., nice but... | 01/01/70 00:00 | |
| Those are actually PALs not CPLDs | 01/01/70 00:00 | |
| ATF750CL for PT clocks | 01/01/70 00:00 | |
| ATF750 | 01/01/70 00:00 | |
| ATF750C ? | 01/01/70 00:00 | |
| Yes, Jim You are exactly right. | 01/01/70 00:00 | |
| Can I suggest | 01/01/70 00:00 | |
| ATDH1150USB | 01/01/70 00:00 | |
| Update : ATDH1150VPC | 01/01/70 00:00 | |
Thanks JIM | 01/01/70 00:00 |