For each product that we make we have to create a test jig. Some products are simple (a relay in a housing) and some run to micros with 20-30 ICs. Almost always the test jig implements a functional test that theoretically checks each function and the provides a go/no-go output. Some jigs are computerized with external PCs, some use the intelligence of the embedded micro and some are simply switches that stimulate the DUT.

We have just had our %&*%$# ISO9000 audit and the auditor wanted some verification that any test jig was working. I would like to say that all the test jigs have been designed so that they would never pass a failed unit when the jig fails. While we could try and implement this in future test jigs, I am not sure I could guarantee that all the jigs are like that now. One proposed solution would be a good and bad sample unit, but that is fraught with problems- maintaining the revision of the samples, tracking the samples when the jigs go to subcontractors, failure of the good sample and all of this still does not check the bed of nails (where used). On computerized systems I suppose we could add circuitry to connect the DA to the AD and the digtals as well, but what guarantees that the checking circuitry is OK and this still doesn't check the bed of nails.

Anyone have any experience/thoughts on this?

-Aubrey