| ??? 10/28/08 11:28 Read: times |
#159401 - I have company.. Responding to: ???'s previous message |
.. Or so it look when it comes to SPI interface problems.
Just look at the timing diagram below with which I am struggling right now : 
Every SPI transaction is made of 13 clock cycles : 3 cycles : Preamble 8 cycles : Data 1 cycle : Status byte from the slave SDO (0x0 = OK; 0x01 = Retry ) 1 cycle : minimum idle time before next transaction. If you check the timing info. you will find the value for "T7" the Output Valid Time for the Status byte from the slave as 20ns max. I am clocking the SPI interface with a 250ns clock pulse and so far have not been able to read the status byte OK. All the other timings have "minimum" values specified and this one parameter alone has a "maximum value ". And the FTDI chip has a 12MHz maximum clock spec. for the SPI interface. Any tips to over come this ( apart from speeding up the clock like crazy ) ? Matter posted to FTDI support but no response. Thanks Raghu |
| Topic | Author | Date |
| SPI is a free for all ?? | 01/01/70 00:00 | |
| Danger to use block sizes not n*8 bits | 01/01/70 00:00 | |
| The non-standard, standard | 01/01/70 00:00 | |
| Master is easy, slave is pure hell | 01/01/70 00:00 | |
| control by chip select | 01/01/70 00:00 | |
| Correct | 01/01/70 00:00 | |
| Now you know why Philips (now NXP) ... | 01/01/70 00:00 | |
| Yes. | 01/01/70 00:00 | |
| What was the incompatibility? | 01/01/70 00:00 | |
| Instruction length. | 01/01/70 00:00 | |
| Bad knowledge of that EEPROM manufacturer | 01/01/70 00:00 | |
| Oh the irony. | 01/01/70 00:00 | |
| No Analogue Irony At All | 01/01/70 00:00 | |
| I have company.. | 01/01/70 00:00 | |
| Your T7 | 01/01/70 00:00 | |
| Simple interpretation | 01/01/70 00:00 | |
| FTDI | 01/01/70 00:00 | |
I have company | 01/01/70 00:00 |