those Xilinx memory controller IP cores ...

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??? 08/14/07 22:22 Read: times	#143291 - those Xilinx memory controller IP cores ... Responding to: ???'s previous message
	... suck. As in, "suck eggs." It's always easier to write your own. That way, you ensure that the interface to the memory matches your specific requirements, rather than having to make it match the Xilinx core's weird interface. An SDRAM or DDR SDRAM interface in VHDL for an FPGA is a homework assignment for seniors. -a

List of 9 messages in thread

Topic Author Date
DDR SDRAM Controller              01/01/70 00:00
   A Response              01/01/70 00:00
      Too complex              01/01/70 00:00
   How about this for some ideas?              01/01/70 00:00
      those SIMMs are not SDRAM!              01/01/70 00:00
   the xilinx example code              01/01/70 00:00
      maybe it is not such a good idea ...              01/01/70 00:00
         will let you know              01/01/70 00:00
      those Xilinx memory controller IP cores ...              01/01/70 00:00

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Topic	Author	Date
DDR SDRAM Controller		01/01/70 00:00
A Response		01/01/70 00:00
Too complex		01/01/70 00:00
How about this for some ideas?		01/01/70 00:00
those SIMMs are not SDRAM!		01/01/70 00:00
the xilinx example code		01/01/70 00:00
maybe it is not such a good idea ...		01/01/70 00:00
will let you know		01/01/70 00:00
*those Xilinx memory controller IP cores ...*		01/01/70 00:00