| ??? 08/13/07 12:18 Read: times |
#143158 - the xilinx example code Responding to: ???'s previous message |
You'll find that one of the major problems with interfacing fast memory is keeping the signals in phase with the clock, even very carefull PCB layout still will not ensure that al the signals to the SDRAM are in phase which is why the xilinx example code makes use of the delay locked clock which allows the transmission delay introduced by the PCB traces to be cancelled out.
there are some very informative white papers about this and other issues when using high speed signals available on the xilinx website. |
| Topic | Author | Date |
| DDR SDRAM Controller | 01/01/70 00:00 | |
| A Response | 01/01/70 00:00 | |
| Too complex | 01/01/70 00:00 | |
| How about this for some ideas? | 01/01/70 00:00 | |
| those SIMMs are not SDRAM! | 01/01/70 00:00 | |
| the xilinx example code | 01/01/70 00:00 | |
| maybe it is not such a good idea ... | 01/01/70 00:00 | |
| will let you know | 01/01/70 00:00 | |
those Xilinx memory controller IP cores ... | 01/01/70 00:00 |