| ??? 08/10/07 22:11 Read: times |
#143078 - DDR SDRAM Controller |
I'm attempting a memory interface controller using FPGA and VHDL to interface the MT46M32V16 DDR SDRAM on Spartan3e development board.
Doing some research I found that Xilinx give a free Memory Interface Generator (MIG) core to generate all the required code for memory refreshing. They also generate code example for the Spartan3e development board. Looking at the generated files, they were too many and I got lost trying to figure what they did, and thought it might be easier to do my own DDR SDRAM controller. I did read alot of application notes for interfacing the MT46M32V16 and I'm in the process of reading the datasheet now. Do the pros suggest I learn how to use the MIG or should I proceed the hard way doing the complex DDR SDRAM interface from scratch? Mahmood |
| Topic | Author | Date |
| DDR SDRAM Controller | 01/01/70 00:00 | |
| A Response | 01/01/70 00:00 | |
| Too complex | 01/01/70 00:00 | |
| How about this for some ideas? | 01/01/70 00:00 | |
| those SIMMs are not SDRAM! | 01/01/70 00:00 | |
| the xilinx example code | 01/01/70 00:00 | |
| maybe it is not such a good idea ... | 01/01/70 00:00 | |
| will let you know | 01/01/70 00:00 | |
those Xilinx memory controller IP cores ... | 01/01/70 00:00 |