| ??? 08/13/07 08:08 Read: times |
#143150 - Too complex Responding to: ???'s previous message |
Joseph Hebert said:
Salaam Mahmood,
On the other hand, I felt bad watching your question drift down into the dark grey without any responses. I didn't want you to think we were all ignoring you. So I posted this response. Look at it on the bright side. At least now your question will get moved back to the top of the list. Maybe someone who didn't see it the first time, and who knows enough to answer your question, will see it this time and respond. Good luck, Joe Many thanks Joe you are too sweet. I read all documentation about DDR SDRAM and how to control it. Then realized the complexity of doing it from scratch and thats why no one responded!, I read all about the MIG and how to use it, so why reinvent the wheel , The MIG takes care of all the complexity controlling the DDR SDRAM and timing including propagation delay caused by track lengths. I'm using the MIG now and problem solved. Andy I searched the forum before posting and visited the exact link you posted. Modern DDR SDRAMs are very fast and complex devices where the data valid window for read operation is about 0.7 nsec for DDR SDRAMs running at 400 Mb/s and 0.14 nsec for DDR2 devices running at 667 Mb/s. Mahmood |
| Topic | Author | Date |
| DDR SDRAM Controller | 01/01/70 00:00 | |
| A Response | 01/01/70 00:00 | |
| Too complex | 01/01/70 00:00 | |
| How about this for some ideas? | 01/01/70 00:00 | |
| those SIMMs are not SDRAM! | 01/01/70 00:00 | |
| the xilinx example code | 01/01/70 00:00 | |
| maybe it is not such a good idea ... | 01/01/70 00:00 | |
| will let you know | 01/01/70 00:00 | |
those Xilinx memory controller IP cores ... | 01/01/70 00:00 |