| ??? 10/03/06 03:39 Read: times |
#125675 - Yes, that's standardly used in such an application Responding to: ???'s previous message |
Richard said:
There are numerous techniques, but the easiest to understand is the PLL synthesizer. Motorola made a series of PLL-based frequency synthesizers, MC14515x, which had a number of versions. These, like any frequency synthesizer, take a reference frequency from a crystal timebase, and a VCO, and divide them down, separately of course, to a common nominal frequency, and then phase-compare them in order to generate an error voltage with which to steer the VCO to the precise frequency required from the divider. By using a high enough crystal frequency and a sufficiently flexible divider chain one can wind up with a very good approximation of the desired frequency. That's probably as good an approach as any. In my archive I have a circuit which does exactly that: A 3.2768MHz crystal feeds a CD4060, which divides the oscillation down to 200Hz. By the help of CD4046 PLL-chip, programmable dividers CD4569 and CD4522 and a BCD-switch this frequency is multiplied by 440,441,...,449. Afterwards the resulting frequency is divided again by factor 200, to provide a frequency of 440Hz to 449Hz in 1Hz steps. The introduction of intermediate frequency of 200Hz is to heavily speed up the settling time of PLL, when changing the frequency at BCD-switch. Without this intermediate frequency one would have to wait several seconds after a change. Kai |
