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???
09/05/06 23:51
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#123717 - It does depend on the instruction set.
Responding to: ???'s previous message
The old bipolar (IIL) Signetics 8x300 had only 8 instructions, so it was definitely a RISC. Of course some of the instructions were quite powerful. IIRC, it could fetch a byte, and it with one quantity, OR it with another, and XOR the result with a third, shift/rotate it a bit one way or the other, then write it to some destination, all in one stroke. The CPU had no internal resources to speak of, other than an ALU and execution unit. Look up the old beastie, check out its environment, and then compare what it could do in its 250 ns cycle time as opposed to what any of the 805x's can do in 250 ns. It may surprise you! You'll have to excuse its lack of bells and whistles, though. It did use external code and data memory, despite its Harvard architecture.

RE


List of 28 messages in thread
TopicAuthorDate
motorola versus 8051            01/01/70 00:00      
   Nebulous question            01/01/70 00:00      
   all            01/01/70 00:00      
      Wile E. Coyote            01/01/70 00:00      
   It's not a 65HC11! It's 68HC11!            01/01/70 00:00      
      ergo...            01/01/70 00:00      
         QED            01/01/70 00:00      
            QED ??            01/01/70 00:00      
               Q.E.D.            01/01/70 00:00      
                  QEF            01/01/70 00:00      
                  Maarten has got it right            01/01/70 00:00      
                     Latin... and I thought this was an english forum            01/01/70 00:00      
                        You've got to expand your horizons.            01/01/70 00:00      
                           No way... I\'m going to be in missery...            01/01/70 00:00      
                              Latin is more useful than C?            01/01/70 00:00      
               QED            01/01/70 00:00      
               QED v Q.E.D.            01/01/70 00:00      
   MIPS?            01/01/70 00:00      
      Processing power            01/01/70 00:00      
         instruction set            01/01/70 00:00      
         Architecture and Instruction Set            01/01/70 00:00      
      not really            01/01/70 00:00      
         It does depend on the instruction set.            01/01/70 00:00      
            RISC?            01/01/70 00:00      
               RISC!            01/01/70 00:00      
                  one instr. / cycle            01/01/70 00:00      
               multiple instrcutions per cycle            01/01/70 00:00      
                  None of this stops the mfg from calling it a RISC            01/01/70 00:00      

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