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???
09/03/06 14:33
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#123601 - Architecture and Instruction Set
Responding to: ???'s previous message
It absolutely would depend on architecture, but if the metric is reduced to the mean number of cycles per instruction, any architectural benefits will be implicit in that number. Then all one needs is the clock speed and one can calculate MIPS.

But Maarten raises a good point, which emphasises your point about architecture. If one processor can execute in a single instruction, by virtue perhaps of specialized hardware, a task that requires three instructions on another processor, it doesn't matter if the second processor is performing twice the MIPS. It still takes the second processor longer to execute the same task than the "slower" processor.

DRAT!!! Erik was right again! Don't you hate it when that happems. I guess it really does depend on which processor is most suited to a particular task.

(P.S. Erik, The misspelling is for you. ;-))

List of 28 messages in thread
TopicAuthorDate
motorola versus 8051            01/01/70 00:00      
   Nebulous question            01/01/70 00:00      
   all            01/01/70 00:00      
      Wile E. Coyote            01/01/70 00:00      
   It's not a 65HC11! It's 68HC11!            01/01/70 00:00      
      ergo...            01/01/70 00:00      
         QED            01/01/70 00:00      
            QED ??            01/01/70 00:00      
               Q.E.D.            01/01/70 00:00      
                  QEF            01/01/70 00:00      
                  Maarten has got it right            01/01/70 00:00      
                     Latin... and I thought this was an english forum            01/01/70 00:00      
                        You've got to expand your horizons.            01/01/70 00:00      
                           No way... I\'m going to be in missery...            01/01/70 00:00      
                              Latin is more useful than C?            01/01/70 00:00      
               QED            01/01/70 00:00      
               QED v Q.E.D.            01/01/70 00:00      
   MIPS?            01/01/70 00:00      
      Processing power            01/01/70 00:00      
         instruction set            01/01/70 00:00      
         Architecture and Instruction Set            01/01/70 00:00      
      not really            01/01/70 00:00      
         It does depend on the instruction set.            01/01/70 00:00      
            RISC?            01/01/70 00:00      
               RISC!            01/01/70 00:00      
                  one instr. / cycle            01/01/70 00:00      
               multiple instrcutions per cycle            01/01/70 00:00      
                  None of this stops the mfg from calling it a RISC            01/01/70 00:00      

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