| ??? 09/05/06 15:47 Read: times Msg Score: +1 +1 Good Answer/Helpful |
#123680 - not really Responding to: ???'s previous message |
If so, then wouldn't the answer depend on the mean number of clock cycles per instruction for each processor, and the speed of the oscillator/crystal driving it?
If you applied that, then a poorly chosen RISC processor would, in all cases, win over a well chosen CISC. 'Instructions' does not mean diddlysquat, time to do the job does. That is where architecture, instruction set and all those other application dependent factors come in. Erik |
| Topic | Author | Date |
| motorola versus 8051 | 01/01/70 00:00 | |
| Nebulous question | 01/01/70 00:00 | |
| all | 01/01/70 00:00 | |
| Wile E. Coyote | 01/01/70 00:00 | |
| It's not a 65HC11! It's 68HC11! | 01/01/70 00:00 | |
| ergo... | 01/01/70 00:00 | |
| QED | 01/01/70 00:00 | |
| QED ?? | 01/01/70 00:00 | |
| Q.E.D. | 01/01/70 00:00 | |
| QEF | 01/01/70 00:00 | |
| Maarten has got it right | 01/01/70 00:00 | |
| Latin... and I thought this was an english forum | 01/01/70 00:00 | |
| You've got to expand your horizons. | 01/01/70 00:00 | |
| No way... I\'m going to be in missery... | 01/01/70 00:00 | |
| Latin is more useful than C? | 01/01/70 00:00 | |
| QED | 01/01/70 00:00 | |
| QED v Q.E.D. | 01/01/70 00:00 | |
| MIPS? | 01/01/70 00:00 | |
| Processing power | 01/01/70 00:00 | |
| instruction set | 01/01/70 00:00 | |
| Architecture and Instruction Set | 01/01/70 00:00 | |
| not really | 01/01/70 00:00 | |
| It does depend on the instruction set. | 01/01/70 00:00 | |
| RISC? | 01/01/70 00:00 | |
| RISC! | 01/01/70 00:00 | |
| one instr. / cycle | 01/01/70 00:00 | |
| multiple instrcutions per cycle | 01/01/70 00:00 | |
None of this stops the mfg from calling it a RISC | 01/01/70 00:00 |