Actually, it's in VHDL, as we use VHDL at the day job (previous job used Verilog). I'd go bonkers if I tried to use both languages at the same time. It's bad enough going from C to VHDL. It's a LOT worse going back and forth between C and Verilog.

(BTW: I don't subscribe to that notion that Verilog is so much like C that a C programmer can just pick it up and do FPGAs. The only similiarities are superficial, like operators and certain syntactical idioms. Otherwise, thinking that Verilog is C is a recipe for disaster.)

Anyways, I'll post it over the weekend. It uses a small part of an XC3S200; it'll easily fit into an XC3S50. The C8015F340 SYSCLK out provides the FPGA clock at 48 MHz, and I use a DCM to divide that down to 4.8 MHz for the GLCD controller stuff. The controller has an address counter and logic to generate the pixel clock (1.2 MHz) and line and frame syncs.

I have to write a coherent description of what I'm doing, as the memory access is somewhat goofy. This is because the LCD has four quadrants, each 240x64 and the controller loads one pixel per quadrant with every pixel clock. It took a bit of playing and simulating to sort it all out.

Right now, my micro application is a simply VT-100-style terminal display. I had to build a character map! (It's in code space.) I need to be a bit more clever to make it display images. Maybe I'll make it into a big LCD simulation of a Nixie clock and a 'Scope Clock!

-a