| ??? 05/20/10 06:47 Read: times |
#176051 - I prefer < 0.5% Responding to: ???'s previous message |
UARTS that isn't using 16x overclocking are still working reasonably well.
They will normally trig the start bit from the flank, instead of polling for the start bit. But not doing a majority vote on the bit values makes them more affected by noise. I don't accept a baudrate error of more than 0.5% since that is just one of multiple accumulating error sources. I may allow 1% when I know that the used baudrates will be low. The start bit is normally polled at 16x baudrate. But noise may delay the detection of the start bit one or two samples. Rise and fall times affects the signal. In a number of situations, the rise and fall times are long because the used driver is bandwidth-limited to reduce the EMI. Having a driver bw-limited for max 115200 baud and running at 115200 baud most definitely means that the margins for baudrate errors needs to take this into account. Sender and receiver may have baudrate errors in reverse direction, doubling the effective baudrate error. And since we are talking about a statistical function, and a single-ended protocol, it is best to err on the safe side. |
| Topic | Author | Date |
| Baud RateTolerance? | 01/01/70 00:00 | |
| acceptable baud-rate error | 01/01/70 00:00 | |
| 100% ?? | 01/01/70 00:00 | |
| 2.5% | 01/01/70 00:00 | |
| whoa!! | 01/01/70 00:00 | |
| I prefer < 0.5% | 01/01/70 00:00 | |
| the method | 01/01/70 00:00 | |
| skew/asymmetry | 01/01/70 00:00 | |
| Asymmetry | 01/01/70 00:00 | |
| ZERO | 01/01/70 00:00 | |
| So do I... | 01/01/70 00:00 | |
| Not always possible to select crystal just for UART | 01/01/70 00:00 | |
| In reference to the above: | 01/01/70 00:00 | |
| Thank you all. | 01/01/70 00:00 | |
| Try a test with a PC and Sqr Sig Gen | 01/01/70 00:00 | |
| likely a wromg approach | 01/01/70 00:00 | |
| Maxim AN-2141 | 01/01/70 00:00 | |
link and comment | 01/01/70 00:00 |